1. Field of the Invention
The present invention relates to a semiconductor memory device comprising flip-flop memory cells.
2. Description of the Prior Art
With the recent process miniaturization, there have been rapidly growing tendencies toward a smaller-area semiconductor integrated circuit and a lower power source voltage. Under the adverse effects thereof, in a semiconductor memory device comprising flip-flop memory cells such as, e.g., a static random access memory (SRAM), it has become extremely difficult to design a memory cell having stable characteristics due to variations in the characteristics of individual transistors composing the memory cell and the lower power source voltage. As a result, a lower production yield of the semiconductor memory device resulting from the degraded operation margins of the memory cell has presented a problem.
The operation margins of the memory cell mentioned herein include a write margin showing the ease of writing during data writing, a static noise margin which is a margin for noise during data reading or data holding, and a cell current showing a speed margin during data reading.
FIG. 12 is a view showing a memory cell 400 which is a typical flip-flop SRAM memory cell composed of CMOS transistors. In the memory cell 400 shown in FIG. 12, QN1 and QN2 denote drive transistors, QN3 and QN4 denote access transistors, QP1 and QP2 denote load transistors, WL denotes a word line, BL and BLX denote bit lines, VDDM denotes a High-data-holding power source (which will be described later), and VSS denotes a ground power source.
The load transistor QP1 and the drive transistor QN1 constitute an inverter, while the load transistor QP2 and the drive transistor QN2 constitute an inverter. The inverters have respective input/output terminals connected in a cross-coupled configuration to compose a flip-flop. The respective output terminals of the individual inverters are referred to herein as data storage nodes. A power source from which power is supplied to the respective sources of the load transistors QP1 and QP2 is referred to as the High-data-holding power source. A power source from which power is supplied to the drive transistors QN1 and QN2 is referred to as a Low-data-holding power source.
The respective gate terminals of the access transistors QN3 and QN4 are each connected to the same word line WL. The drain terminal of the access transistor QN3 is connected to the bit line BL, while the drain terminal of the access transistor QN4 is connected to the bit line BLX. The respective source terminals of the access transistors QN3 and QN4 are connected to the input/output terminals of the inverters mentioned above.
The writing of data to the SRAM memory cell of FIG. 12 is implemented by shifting the potential on either one of the bit lines BL and BLX which have been each precharged to a High level (H level) to a Low level (L level) from the H level in a state (referred to as an active state) where the word line WL has been shifted from the L level to the H level.
FIG. 13 shows a schematic view of a memory cell array in which the memory cells 400 are arranged on an array. Each of the memory cells in the memory cell array is accessed in each of row and column directions to be selected by selecting one of a plurality of bit-line selection circuits and one of a plurality of word line drivers, which are not shown. An arrangement of the memory cells in the column direction in which each of the bit lines is routed is referred to as a column.
A description will be given to characteristics related to the operation margins of each of the SRAM memory cells.
A margin during data writing is shown by the voltage of the bit line for performing writing to one of the memory cells. The operation of writing data to the SRAM memory cell is performed by inverting the state of the flip-flop composing the memory cell (it is to be noted that, when the same data as the data to be written has been stored in advance in the memory cell, the state of the flip-flop is not inverted). At this time, the critical potential of the bit line which allows the inversion of the state of the flip-flop of the memory cell is referred to as the write margin.
For example, when the write margin is low, the margin (static noise margin) for erroneous writing due to bit-line noise or the like increases. On the other hand, when the potential of the bit line has not reached a sufficiently low level, the flip-flop cannot be inverted.
Conversely, when the write margin is high, the time required for data writing is reduced, but the margin for erroneous writing (static noise margin) decreases.
A low write margin indicates that the state of the flip-flop composing the memory cell is immune to inversion due to the bit-line noise or the like during a read operation, i.e., the static noise margin increases. On the other hand, a high write margin indicates that the state of the flip-flop composing the memory cell is susceptible to inversion during a read operation, i.e., the static noise margin decreases.
When the potential on the word line WL is increased or the threshold of each of the drive transistors or the access transistors is lowered with the view to increasing the reading speed, data at the storage nodes of the flip-flop is more susceptible to the influence of the bit-line noise so that the static noise margin lowers.
There is also the cell current as a speed-related margin. The cell current is a current value in the selected memory cell when the drive transistor having a drain connected to the Low-data storage node discharges the bit line via the access transistor till it reaches the potential VSSM which is the source potential. As the cell current is larger, the speed of discharging the selected bit line is higher and the speed of amplifying the potential difference in the bit line pair and reading data is higher. However, when the cell current is increased by reducing the threshold of each of the memory cell transistors or increasing the word line potential, the susceptibility to the bit-line noise increases and the static noise margin decreases.
Thus, the write margin, the static noise margin, and the cell current (speed margin) have contradictory characteristics such that, when one of the characteristics is to be satisfied, the other characteristics decrease.
Because of the contradiction, it has been proposed to improve at least one of the characteristics. For example, a semiconductor memory device has been reported which is constructed such that the word line potential is lowered only slightly from the conventional power source potential in order to improve the static noise margin. For example, it has been attempted to slightly lower the word line potential from the power source potential to improve the static noise margin (see, e.g., 2006 Symposium on VLSI Circuits Digest of Technical Papers, pp. 20-21, which document will be hereinafter referred to as Non-Patent Document 1).
In addition, a semiconductor memory device has also been known which is constructed in order to satisfy only the write margin such that the High-data-holding power source of the memory cell is controlled to be lower during a write operation to provide an improved write margin (see, e.g., Japanese Laid-Open Patent Publication No. SHO 55-64686, which document will be hereinafter referred to as Patent Document 1).
FIG. 14 shows an example of potentials at the individual terminals of one of the memory cells when both of the techniques disclosed in Non-Patent Document 1 and Patent Document 1 shown above are used.
During a non-selection period, a potential Vdd (1.1 V), which is a power-source potential, is supplied to the High-data-holding power source VDDM of each of the memory cells and to the bit line pair (BL, BLX), while a potential Vss (0 V) is supplied to the Low-data-holding power source VSSM of the memory cell and to the word line (WL).
During a write operation, a potential (1.0 V) slightly lower than the potential Vdd is supplied to the word line (WL), while a potential (0.7 V) lower than the potential Vdd is supplied to each of the High-data-holding power sources in the selected column. Although data writing to the selected memory cell becomes difficult by thus slightly lowering the word line potential, the gate potential of each of the access transistors of the non-selected memory cells arranged in the row direction under the word line is lowered with the view to attempting to prevent data destruction by increasing the static noise margin of each of the non-selected memory cells even slightly, and then the power source potential of the selected column (in the column direction) is lowered to improve the write margin of the selected memory cell.
On the other hand, during a read operation, a potential (1.0 V) lower than the potential Vdd is supplied to the word line (WL) in the same manner as during the write operation, the bit line precharged in advance to the power source potential by the drive transistor connected to the Low-data storage node in the memory cell is discharged, and data is read by amplifying the potential difference produced between in bit line pair.
Although the gate potential of the access transistor is reduced and the cell current of the selected memory cell is lowered by thus slightly lowering the word line potential, it is attempted to increase the static noise margin of each of the non-selected memory cells under the selected word line even slightly and thereby prevent data destruction.
In general, when the threshold voltage of each of memory transistors is controlled to be higher than that of each of logic transistors other than the transistors of the memory cells as shown in FIG. 14, the stored data is less likely to be inverted in response to noise than in the case where transistors each having the same threshold voltage as the logic transistors are used for the memory cells. In other words, the static noise margin is thereby increased.
However, in a structure in which an improvement in static noise margin is attempted by lowering only the word line potential such as the semiconductor memory device disclosed in Non-Patent Document 1 shown above, a write operation to the memory cell is also to be performed with the same word line potential. As the word line potential is lowered, the static noise margin is more improved. However, there is the problem that data writing during a write operation becomes difficult, while the cell current during a read operation decreases to reduce the reading speed.
It is also expected that, as variations in the thresholds of transistors further increase with future process miniaturization, the static noise margin of the SRAM memory cell further decreases. To improve the static noise margin in accordance with the expectation, it is necessary to further lower the word line potential. However, when the word line potential is further lowered, the problem is encountered that the Low level cannot be written in the memory cell even if the bit line potential is lowered to 0 V during a write operation, while the reading speed is further reduced.
On the other hand, in a semiconductor memory device in which the High-data-holding power source voltage for the memory cell is controlled such as the semiconductor memory device disclosed in Patent Document 1 shown above, the write margin is improved but, when the High-data-holding power source voltage for the memory cell is controlled to be lower during data writing, the High-data-holding power source voltage for the non-selected memory cells in the same column is also reduced. As a result, the problem occurs that the power source voltage for holding data in the non-selected memory cells decreases to result in data destruction.
There is also the problem that, although the static noise margin is increased by increasing the threshold voltage of each of the memory cell transistors to a level higher than that of the threshold voltage of each of the logic transistors, the write margin and the cell current are conversely reduced by the increased threshold voltage.
In addition, to increase the threshold voltage, the process step of adjusting an impurity only for the threshold adjustment of the memory cells is necessary, which leads to the problem of higher process cost.
There is the further problem that, when the impurity in each of the memory cell transistors is increased to increase the threshold voltage thereof, variations in the threshold voltages of the transistors increase to reduce the operation margins of the memory cells.
Thus, in the conventional semiconductor memory device, when one of the operation margins of the SRAM memory cell is to be improved, the other operation margins deteriorate under the constraints of the tradeoff relations among the operation margins. This results in the problem that, to satisfy all of the operation margins, optimization design should be performed under operating conditions in an extremely narrow range.
That is, to optimize the word line potential, it is necessary to optimize the contradictory characteristics of: (1) static noise margin; (2) write margin; and (3) cell current. There is also the problem that, to obtain a margin during data writing, the contradictory characteristics of: (2) write margin; and (4) data holding voltage should be optimized.
There is the further problem that, as variations in the threshold voltages of transistors increase with future process miniaturization, a design range capable of satisfying these characteristics is further narrowed, and the design of the SRAM memory cell becomes difficult.